Hi ,
are there still available header files
previously available at http://opendreambox.org/ ?
Here is a a part of a file
1 /***************************************************************************
2 * Copyright © 1999-2006, Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Module Description:
18 * DO NOT EDIT THIS FILE DIRECTLY
19 *
20 * This module was generated magically with RDB from a source description
21 * file. You must edit the source file for changes to be made to this file.
22 *
23 *
24 * Date: Generated on Wed Jul 12 12:00:32 2006
25 * MD5 Checksum 65dc148f276b8e1325bb5f85be0ccf82
26 *
27 * Compiled with: RDB Utility combo_header.pl
28 * RDB Parser 3.0
29 * unknown unknown
30 * Perl Interpreter 5.006
31 * Operating System linux
32 *
33 * Revision History:
34 *
35 * $brcm_Log: /magnum/basemodules/chp/7401/rdb/c0/bchp_memc_0_ddr.h $
36 *
37 * Hydra_Software_Devel/1 7/14/06 12:49p jasonh
38 * PR 22628: Initial version
39 *
40 ***************************************************************************/
42 #ifndef BCHP_MEMC_0_DDR_H__
43 #define BCHP_MEMC_0_DDR_H__
45 /***************************************************************************
46 *MEMC_0_DDR - Memory Controller DDR IOBUF Registers
47 ***************************************************************************/
48 #define BCHP_MEMC_0_DDR_IOBUF_REV_ID 0x00106800 /* Memory Controller IOBUF Revision ID Register. */
49 #define BCHP_MEMC_0_DDR_PAD_SSTL_MODE 0x00106804 /* Pad Mode Control Register */
50 #define BCHP_MEMC_0_DDR_DQ_PAD_CNTL 0x00106808 /* Data Pad Control Register */
51 #define BCHP_MEMC_0_DDR_DQS_PAD_CNTL 0x0010680c /* DQS Pad Control Register */
52 #define BCHP_MEMC_0_DDR_CMD_PAD_CNTL 0x00106810 /* Command Pad Control Register */
53 #define BCHP_MEMC_0_DDR_CLK_PAD_CNTL 0x00106814 /* Clock Pad Control Register */
54 #define BCHP_MEMC_0_DDR_PLL_FREQ_CNTL 0x00106818 /* DDR PLL frequency control register */
55 #define BCHP_MEMC_0_DDR_PLL_CLK_ADDR_PHASE_CNTRL 0x0010681c /* Interpolator Phase Control Register */
56 #define BCHP_MEMC_0_DDR_DQ_DQS_PHASE_CNTRL_EVEN 0x00106820 /* Interpolator Phase Control Register */
...
...
...
There were files not only for BCM7401 but also for BCM7405 and other CPUs
Does anyone have those files?
Thank you